1. Field of the Invention
The present invention relates generally to a semiconductor device, and more particularly, to a method of using drain coupling to suppress the second bit effect of localized split floating gate devices with two-bit operation capability.
2. Description of the Related Art
The use of semiconductor devices with multiple bit operation capability leads to reduce the volume occupied by the devices and produce dense semiconductor structures. FIG. 1 illustrates a cross-sectional view of a conventional floating gate Nitride Read Only Memory (NROM) cell with two bits operation capability. The NROM cell 100 includes a P-well substrate 110 with doped source 120 and drain 130. A silicon nitride layer 150 is sandwiched between two oxide layers 140 and 160 which are disposed over the substrate 110. A gate conductor 170 is disposed over the oxide layer 160, and a channel 115 is formed under the oxide layer 140 between drain 130 and source 120.
A NROM cell can be electrically programmed, read, and erased. The programming of the NROM cell 100 generates hot electrons in the channel 115. A fraction of these hot electrons gain enough energy to surmount the barrier of the oxide layer 140 and become trapped in the silicon nitride layer 150. The trapped charge will move to the region in the layer 150 near drain 130. Since the silicon nitride layer 150 is non-conductive, the NROM cell 100 can be programmed to have hot charges gathered at both ends of the layer 150 by interchanging the role of the source/drain terminal. The stored charge at the left end of the layer 150 is considered as the bit-1 180 whereas the stored charge at the right end of the layer 150 is considered as the bit-2 190.
When a NROM cell is read, the presence or absence of stored charge is determined by sensing the change is its threshold voltage Vt. The more the stored charge, the higher the threshold voltage Vt. The two bits operation of the NROM cell 100 can be realized by using a reverse read scheme, which is performed in the reverse direction compared to the programming.
The second bit effect, the unique phenomenon in a two-bit storage memory cell is caused by the interaction between the bit-1 180 and the bit-2 190 during a reverse read operation. As shown in FIG. 1, a read voltage Vread is applied to the drain terminal when the bit-1 180 of the NROM cell 100 is read using the reverse read scheme. If the bit-1 180 and the bit-2 190 are programmed to low threshold voltages, the potential barrier created by the bit-2 190 while reading the bit-1 180 can be screened out by a suitable Vread. Thus, the bit-1 180 can be read successfully. However, if the bit-2 190 is programmed to a high threshold voltage state and the bit-1 180 is retained at a low threshold voltage state, as the threshold voltage of the bit-2 190 increases, the read voltage Vread for the bit-1 180 becomes insufficient to overcome the potential barrier created by the bit-2 190. Consequently, the threshold voltage of the bit-1 180 is pulled up as a result of the increasing threshold voltage of the bit-2 190. This phenomenon is called the second bit effect.
The second bit effect is a severe problem for a two-bit semiconductor device because it decreases the read sense margin and makes the multiple level cell (MLC) operation difficult to operate. In addition, the second bit effect causes the degradation of the sub-threshold swing.
In view of the foregoing, there is a need for a method of suppressing the second bit effect for a two-bit semiconductor device during its reverse read operation.